This application is based upon and claims priority of Japanese Patent Application No. 2001-261967, filed on Aug. 30, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to an amplification circuit, and particularly to an amplification circuit for outputting from its output terminal a voltage in accordance with voltages inputted to its first and second input terminals.
2. Description of the Related Art
FIG. 7A shows a circuit of an operational amplifier in a prior art.
An n-channel MOS (metal-oxide-semiconductor) transistor 702a has a gate connected to a positive logic input terminal IN, a source connected to one end of a constant current source 703, and a drain connected to one end of a load 701a. The other end of the constant current source 703 is connected to a ground potential. The other end of the load 701a is connected to a positive power source potential Vdd.
An n-channel MOS transistor 702b has a gate connected to a negative logic input terminal XIN, a source connected to the aforesaid one end of the constant current source 703, and a drain connected to an output terminal OUT and one end of a load 701b. The other end of the load 701b is connected to the power source potential Vdd.
A positive logic input signal Vin which is inputted to the positive logic input terminal IN and a negative logic input signal Vxin which is inputted to the negative logic input terminal XIN mutually compose differential signals. In other words, both signals are signals whose logics are opposite to each other.
FIG. 7B is a chart showing the operation of the operational amplifier in FIG. 7A. The horizontal axis represents a differential voltage Vinxe2x88x92Vxin and the vertical axis represents currents Isrc and Iout and a voltage Vout. The current Isrc is a current flowing through the current source 703 and is constant regardless of the differential voltage Vinxe2x88x92Vxin. The current Iout is a current flowing through the load 701b and varies lineally in accordance with the differential voltage Vinxe2x88x92Vxin in a predetermined range. The output voltage Vout is a voltage of the output terminal OUT. When a resistance value of the load 701b is shown by R, the output voltage Vout is expressed by the following formula.
Vout=Vddxe2x88x92Ioutxc3x97R 
FIG. 8 shows a circuit of another operational amplifier in the prior art. In this operational amplifier, p-channel MOS transistors 801a and 801b are provided in place of the loads 701a and 701b in FIG. 7A so that the gain of the output voltage Vout can be increased. The p-channel MOS transistor 801a has a source connected to the power source potential Vdd and a drain connected to the drain of the n-channel MOS transistor 702a. The p-channel MOS transistor 801b has a source connected to the power source potential Vdd and a drain connected to the drain of the n-channel MOS transistor 702b. Gates of the transistors 801a and 801b are connected to the drain of the transistor 702a. 
For example, when the positive logic input signal Vin becomes larger, a current flowing through the transistor 801a increases and a voltage of the drain of the transistor 702a decreases. Then, a gate voltage of the transistor 801a decreases and the current flowing through the transistor 801a further increases. As a result, a current flowing through the transistor 801b decreases and an output voltage of the output terminal OUT further increases so that the high gain can be obtained.
FIG. 9 shows a circuit of still another operational amplifier in the prior art. In this operational amplifier, an n-channel MOS transistor 901 is provided in place of the current source 703 of the operational amplifier in FIG. 7A so that the gain of the output voltage Vout can be increased. The transistor 901 has a gate connected to the drain of the transistor 702a, a source connected to the ground potential, and a drain connected to the sources of the transistors 702a and 702b. 
For example, when the positive logic input signal Vin becomes larger, a current flowing through the transistor 702a increases and the voltage of the drain of the transistor 702a decreases. Then, a gate voltage of the transistor 901 decreases and a current flowing through the transistor 901 decreases. As a result, a current flowing through the transistor 702b also decreases and the output voltage Vout of the output terminal OUT increases so that the high gain can be obtained.
The operational amplifier as described above is used for a small-amplitude input circuit so as to receive a signal from the outside and amplify it. Some small-amplitude input circuits receive data and a clock simultaneously.
As shown in FIG. 10, however, a clock 1001 has a high frequency compared with that of data 1002 and, when a waveform becomes deformed due to signal propagation, the signal amplitude becomes smaller. For example, the clock 1001 is a binary logic signal whose low level is 1 V and high level is 2 V, while the data 1002 is a binary logic signal whose low level is 0 V and high level is 3.3 V.
In this case, even if the clock 1001 and the data 1002 start falling simultaneously at time t1, delay time Td occurs between the clock 1001 and the data 1002. In other words, if the amplitude of the clock 1001 and the data 1002 are different, the delay time Td occurs between the clock 1001 and the data 1002. Further, there is a problem that the delay time Td varies depending on the magnitude of the amplitude of the signals.
As shown in FIG. 7B, the aforesaid operational amplifier can output the output voltage Vout in a range from 0 to Vdd V. If the amplitude of the input signals Vin and Vxin are small, the amplitude of the output voltage Vout is also small, and if the amplitude of the input signals Vin and Vxin are large, the amplitude of the output voltage Vout is also large. As shown in FIG. 10, the signal 1001 of 1 to 2 V is outputted and the signal 1002 of 0 to 3.3 V is outputted in accordance with the amplitude of the input signals Vin and Vxin.
It is an object of the present invention to provide an amplification circuit capable of outputting an output voltage having the constant amplitude regardless of the magnitude of the amplitude of an input signal.
According to an aspect of the present invention, provided is an amplification circuit comprising: a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal or a reference potential is connected and a drain to which a first load is connected; a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic input signal, or the reference potential is connected and a drain to which an output terminal and a second load is connected, and pairing up with the first MOS transistor; and a current source to which sources of the first and second MOS transistors are connected, for supplying a constant current to the first and/or second load when the difference in voltage between the first and second input terminals is in a predetermined range, and varying the current to be supplied to the first and/or second load when the difference in voltage is beyond the predetermined range.
The current source supplies the constant current to the first and/or second load when the difference in voltage between the first and second input terminals is in the predetermined range, while varies the current to be supplied to the first and/or second load when the difference in voltage is beyond the predetermined range so that a voltage of the output terminal can be controlled at a constant value when the difference in voltage is beyond the predetermined range. As a result, when the amplitude of the input signal is large, the amplitude is controlled so that an output signal constantly having the same amplitude can be outputted. The amplitude of the output signal becomes constant, which makes it possible to eliminate delay time between signals or to keep the delay time constant.